1. Field of the Invention
The present invention relates to a method of testing a semiconductor apparatus suitable for detecting a defective cell due to a defective standby current or SNM (static noise margin) deficiency.
2. Description of Related Art
Normally, when testing a memory cell such as RAM (Random Access Memory), a BIST (built in self-test) is performed (step S101), a fail bit is read (step S102), and a defective cell is replaced with a redundancy cell by cutting a fuse (step S103), as shown in FIG. 6.
However, in some cases, a cell which places the border of a defective cell and a non-defective cell remains without being replaced. In such a case, there is a problem that memory malfunctioning is likely to occur depending on the LSI use environment, that is, by a temperature or voltage change. Defective modes include a write/read defect caused by the varying threshold of a field-effect transistor constituting a memory cell and an unstable operation caused by the deficiency of SNM, in addition to a leakage defect that has been a problem. These defective modes are aggravated as miniaturization progresses, which raises a problem of a cost increase due to the need for a high-temperature/low-temperature test for reliable removal of a defective cell or the like.
Japanese Unexamined Patent Application Publication No. 2002-93195 (Shiomi) discloses a method of testing a semiconductor apparatus of which object is detecting a defect of a direct-current electricity such as a standby current defect and saving a defective cell. FIG. 7 is a view of an SRAM disclosed by Shiomi. The method of testing a semiconductor apparatus taught by Shiomi aims at identifying and saving a defective cell when a standby current flows in the SRAM due to a minute leakage.
As shown in FIG. 7, a memory cell M1 includes an n-channel MOS transistor 80 and an n-channel MOS transistor 82. The n-channel MOS transistor 80 is connected between a bit line BL1 and a storage node N10, and its gate is connected with a word line WL1. The n-channel MOS transistor 82 is connected between a bit line /BL1 and a storage node N11, and its gate is connected with a word line WL1.
The memory cell M1 further includes an n-channel MOS transistor 74 and an n-channel MOS transistor 78. The source of the n-channel MOS transistor 74 is connected with the ground voltage GNDM of a memory cell array, the drain is connected with a storage node N10, and the gate is connected with a storage node N11. The source of the N-channel MOS transistor 78 is connected with the ground voltage GNDM, the drain is connected with the storage node N11, and the gate is connected with the storage node N10.
The memory cell M1 further includes a p-channel MOS transistor 72 and a p-channel MOS transistor 76. The source of the p-channel MOS transistor 72 is connected with a power supply voltage VCCM for a memory cell array, the drain is connected with the storage node N10, and the gate is connected with the storage node N11. The source of the p-channel MOS transistor 76 is connected with the power supply voltage VCCM, the drain is connected with the storage node N11, and the gate is connected with the storage node N10.
It is assumed that the storage node N11 of the memory cell M1 is coupled with the power supply voltage VCCM of the memory cell array by a resistor R1 to cause short-circuit. The memory cell M1 is capable of controlling the ground voltage GNDP, which is a substrate voltage of the n-channel MOS transistors 74 and 78 that constitute a memory cell of SRAM, independently of the ground voltage GNDM, which is a source voltage. When the storage node N11 is “L”, a through current flows in the pass indicated by the arrow. Since the through current keeps flowing in a standby condition, the semiconductor apparatus has a standby defect. When the standby current defect occurs, GNDP is set lower than GND (back bias). As a result, the drive ability of the n-channel MOS transistors 74 and 78 is weakened by body effect. This enables to detect a defect by a function test. It is therefore possible to identify a defective memory cell and replace the defective cell with a redundancy cell, thereby improving process yield.
However, the method taught by Shiomi only controls a threshold to be higher by applying a back bias. Therefore, although it has a tentative effect that the memory cell which has leakage is easily identified, the method is incapable of detecting the defective mode that becomes more significant as the threshold of the field-effect transistor becomes lower (or a cell current becomes higher), such as an SNM defect.